1. Technical Field
The present invention relates in general to cache controllers in data processing systems and in particular to cache controllers for caches in data processing system. Still more particularly, the present invention relates to layering cache and architectural specific functions within a cache controller for a cache in a data processing system to facilitate definition of generic interfaces which may be translated to specific bus architectures.
2. Description of the Related Art
Data processing systems which utilize a level two (L2) cache typically include a cache controller for managing transactions affecting the cache. Such cache controllers are conventionally implemented on a functional level, as depicted in FIG. 5. For example, a cache controller 502 may include logic 504 for maintaining the cache directory, logic 506 for implementing a least recently used (LRU) replacement policy, logic for managing reload buffers 508, and logic for managing store-back buffers 510. In traditional implementations, the cache is generally very visible to these and other architectural functions typically required for cache controllers, with the result that cache controller designs are specific to a particular processors such as the PowerPC.TM., Alpha.TM., or the x86 family of processors.
In addition to being processor-specific, cache controllers are generally also bus-specific. That is, cache controller implementations are typically specific to protocols governing transactions on the bus between the processor(s) and the cache controller(s). In fact, actions within the cache controller are initiated by bus operations. Thus, the cache controller is closely coupled in both design and operation to the specific buses connected to the cache controller.
Processors employed in data processing systems of the type discussed generally support a significant number of cache management instructions, such as a flush command, data cache block store, etc. Support for these instructions is typically implemented over the cache logic, substantially complicating the cache controller design requirements by imposing special cases for different instructions.
One problem with the prior art approach to implementing cache controllers is the virtual impossibility of defining a generic interface between the cache controller logic and a bus interface unit to a bus. Such a generic interface would be useful since it would allow the cache controller logic to be reused when revising the overall cache controller design for operation with a different processor or bus architecture. Under the prior art approach, the cache controller logic cannot be simply reused independent of any bus interface unit within the cache controller.
It would be desirable, therefore, to implement a cache controller design which permits definition of a generic interface between the cache controller logic and a bus interface unit for the cache controller. It would also be advantageous if the cache controller design simultaneously facilitated reuse of the cache controller logic. Finally, it would be advantageous for the cache controller design to permit implementation of generic interfaces which may be customized depending on the characteristics of particular bus operations.